Performance Modeling Engineer
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Job Details:
Job Description:
We are looking for enthusiastic and highly motivated individual who are passionate about computer architecture, hardware modeling, and system-level performance analysis.
In this role, you will be part of our Architecture Team, contributing to the modeling and evaluation of performance‑critical hardware components for next‑generation FPGAs.
You will work closely with experienced architects and design teams as you explore innovative architectures and help shape our future silicon products.
This is an excellent opportunity for new graduates to develop deep expertise across SoC performance modeling, interconnect analysis, and system‑level architecture.
Key Responsibilities:
Develop and simulate performance models (using C++/SystemC, TLM‑2.0) for critical hardware components and subsystems.
Perform early design space exploration at the FPGA, SoC interconnect, and subsystem levels to help identify optimal Power, Performance, and Cost tradeoffs.
Analyze workloads and data‑movement patterns across modern SoC components, including memory hierarchies, DDR interfaces, PCIe, Ethernet, and embedded processors.
Collaborate closely with architects, designers, and verification teams throughout the product development lifecycle, from concept to silicon bring‑up.
Contribute to performance correlation between high‑level models, cycle‑accurate RTL simulations, and final silicon.
Qualifications:
Strong programming skills in C++ (coursework or projects).
Exposure to SystemC or TLM modeling through classes, internships, or academic projects (preferred, but not mandatory).
Solid understanding of computer architecture fundamentals.
Strong analytical and problem‑solving skills with the ability to learn complex topics quickly.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science, or related fields.